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| report:dvp [2026/06/14 14:45] – [7.4 Design] team5 | report:dvp [2026/06/14 15:45] (current) – team5 |
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The web interface, accessible via QR code, is designed in a minimalist style. After scanning the QR code, users are redirected to the web application's landing page. The CONNECT logo takes center stage here, accompanied by two clickable buttons that lead to the subsequent sections. Within the app, users can choose between composing a message for others or viewing messages written by the community. Our primary focus was to keep the application as simple as possible; we wanted to ensure that both young and old users can navigate it effortlessly. By eliminating the need for logins or complex navigation, we’ve made the experience accessible and time-efficient for everyone. |
The web interface, accessible via QR code, is designed in a minimalist style. After scanning the QR code, users are redirected to the web application's landing page. The CONNECT and share logo takes center stage here, accompanied by two clickable buttons that lead to the subsequent sections. Within the app, users can choose between composing a message for others or viewing messages written by the community. Our primary focus was to keep the application as simple as possible; we wanted to ensure that both young and old users can navigate it effortlessly. By eliminating the need for logins or complex navigation, we’ve made the experience accessible and time-efficient for everyone. |
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| == 7.4.1 Structure == | == 7.4.1 Structure == |
| <figure fig:3d_model_idealVersion> | <figure fig:3d_model_idealVersion> |
| {{ :report:whatsapp_image_2026-06-03_at_14.48.56_2_.jpeg?nolink&800 |}} | {{ :report:whatsapp_image_2026-06-03_at_14.48.56_2_.jpeg?nolink&800 |}} |
| <caption>3D spatial visualization of the fully integrated Connect system within the standard Porto Metro carriage architecture</caption> | <caption>3D spatial visualization of the fully integrated CONNECT and share system within the standard Porto Metro carriage architecture</caption> |
| </figure> | </figure> |
| </WRAP> | </WRAP> |
| **Software** | **Software** |
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| The software architecture of the Connect and Share project facilitates real-time interaction and asynchronous digital connection across two distinct modes of use. | The software architecture of the CONNECT and share project facilitates real-time interaction and asynchronous digital connection across two distinct modes of use. |
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| I. Use Cases and User Stories | I. Use Cases and User Stories |
| III. Component Diagram | III. Component Diagram |
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| Figure {{ref>fig:frontend_flowchart}} depicts the frontend flow of the Connect web interface. Starting from a QR code scan, the browser fetches and renders the website. The user is then presented with two interaction options: writing a message, which is transmitted to the backend, or reading a message, which triggers a random message fetch and displays it on screen. | Figure {{ref>fig:frontend_flowchart}} depicts the frontend flow of the CONNECT and share web interface. Starting from a QR code scan, the browser fetches and renders the website. The user is then presented with two interaction options: writing a message, which is transmitted to the backend, or reading a message, which triggers a random message fetch and displays it on screen. |
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| <WRAP centeralign> | <WRAP centeralign> |
| == 7.6.1 Hardware tests == | == 7.6.1 Hardware tests == |
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| The physical validation of the Connect prototype was executed in a controlled laboratory environment using the benchtop assembly. Each requirement specified during the initial design stage was systematically evaluated. Table {{ref>tab_test_results}} details the comprehensive log of this validation phase, highlighting whether the criteria achieved a Pass (P), a Fail (F), or were deemed Not Applicable (N/A) due to the reduced scope of the laboratory prototype. | The physical validation of the CONNECT and share prototype was executed in a controlled laboratory environment using the benchtop assembly. Each requirement specified during the initial design stage was systematically evaluated. Table {{ref>tab_test_results}} details the comprehensive log of this validation phase, highlighting whether the criteria achieved a Pass (P), a Fail (F), or were deemed Not Applicable (N/A) due to the reduced scope of the laboratory prototype. |
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| <table tab_test_results> | <table tab_test_results> |
| The visual response test resulted in a technical **Fail** due to predictable high-frequency signal artifacts. The prototype utilized a **Seeed 1-meter addressable WS2813 IP65 strip (18W, 5VDC)** connected via its integrated Grove interface. While the strip displayed the programmed color-blending animations accurately under active states, noticeable flickering was captured when the LEDs were idle. Specifically, the first pixel intermittently flashed bright white or random colors, and random color flickers propagated down the line. | The visual response test resulted in a technical **Fail** due to predictable high-frequency signal artifacts. The prototype utilized a **Seeed 1-meter addressable WS2813 IP65 strip (18W, 5VDC)** connected via its integrated Grove interface. While the strip displayed the programmed color-blending animations accurately under active states, noticeable flickering was captured when the LEDs were idle. Specifically, the first pixel intermittently flashed bright white or random colors, and random color flickers propagated down the line. |
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| A thorough electrical diagnosis isolated this issue to a **logic-level mismatch**: the standard ESP32 transmits digital data streams using a $3.3\text{ V}$ CMOS logic level, whereas the WS2813 protocol dictates a high-level input threshold ($V_{IH}$) of at least $0.7 \times V_{DD}$. Powered at $5.0\text{ V}$, the Seeed strip requires a minimum data signal amplitude of $3.5\text{ V}$. Operating at the absolute edge of the noise margin, the $3.3\text{ V}$ data pulses caused the internal shift registers of the first pixels to misinterpret high/low states, causing erratic behaviors. This limitation provides a crucial baseline for future hardware revisions. | A thorough electrical diagnosis isolated this issue to a **logic-level mismatch**: the standard ESP32 transmits digital data streams using a $3.3\text{ V}$ CMOS logic level, whereas the WS2813 protocol dictates a high-level input threshold ($V_{IH}$) of at least $0.7 \times V_{DD}$ [(worldsemiWS2813)]. Powered at $5.0\text{ V}$, the Seeed strip requires a minimum data signal amplitude of $3.5\text{ V}$. Operating at the absolute edge of the noise margin, the $3.3\text{ V}$ data pulses caused the internal shift registers of the first pixels to misinterpret high/low states, causing erratic behaviors. This limitation provides a crucial baseline for future hardware revisions. |
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| **Power and Electrical Distribution (FT-05, PT-04)**\\ | **Power and Electrical Distribution (FT-05, PT-04)**\\ |